Timing Closure Jobs In Antwerpen - 3 Job Positions Available

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Senior FPGA Engineer (VHDL/Verilog)

AGAD Technology ( Schelle VAN )

As a Senior FPGA Engineer, you will contribute to the development of key components of our networking system, including SmartNICs and hybrid optical switches. You will be responsible for designing and optimizing VHDL and/or Verilog implementations.

AGAD Technology 15 days ago

Senior FPGA Engineer (VHDL/Verilog)

AGAD Technology ( Schelle VAN )

Senior FPGA Engineer (VHDL/Verilog) Position: Senior FPGA Engineer (VHDL/Verilog) Location: Schelle, Belgium Industry: Networking Job Type: Full-time Work Arrangement: This role is based in Schelle, Belgium, with the possibility of hybrid work. Applicants must already have

Full-time Debugging Performance testing Timing Closure Python

AGAD Technology 1 day ago

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Image Sensor Digital Design and Verification Engineer

Eyeo ( Antwerpen VAN )

Job Title: Image Sensor Digital Design and Verification Engineer Have you got what it takes to succeed The following information should be read carefully by all candidates. Location: Antwerp, Belgium Reports To: Design Center Manager About

Full-time Low-power Design High-speed Digital Design Timing Closure Architecture EDA

Eyeo 16 hours ago

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Timing Closure Jobs In Antwerpen - 3 Job Positions Available

Senior FPGA Engineer (VHDL/Verilog)

Senior FPGA Engineer (VHDL/Verilog)

Image Sensor Digital Design and Verification Engineer

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